In the 1980s, we were engaged in the design of specialized and embedded computer systems. Starting from the second half of the 80s, we started using hardware description languages. The first such language was HDL FLAG, which we’ve been using in the designing of the 4.601.VZh3 series VLSI set, which included the following microcircuits: 4.601.VZh3-001 – a switch with a delay for the FFT processor, 4.601.VZh3-002 – a memory address generator, 4.601.VZh3-003 – a complex number multiplier, 4.601.VZh3-004 – an automatic detector. When the hardware description language VHDL has been developed in the second half of the 90s, we’ve joined the association for its implementation.

I had to practically master the skills of working in the VHDL language in 1996, when, with the support of a grant from the German academic foundation DAAD, I was engaged in scientific research at the University of Applied Sciences in Nuremberg. I was faced with the task of designing a floating-point pipeline FFT processor. Work on the project occupied all my work and free time. During the execution of the project, several interesting ideas emerged both regarding the processor architecture and design principles that allow to simplify and speed up the design process. Then I mastered the IP core technology, which involves creating models of computer devices suitable for reuse by other designers. At the same time, the idea of creating generators of computer device models appeared, which involves the description in the HDL language of a multifunctional configuration model of a computer device with the possibility of extracting from this model a specialized device focused on a specific application, i.e. IP core. I implemented this idea for the first time when creating a generator of processors of fast orthogonal transformations (FOT) as part of a scientific project carried out at the University of Applied Sciences in Nuremberg in 1997/98 with the financial support of the Bavarian government. The expediency of performing FOT algorithms based on the fast cosine transformation algorithm was substantiated and a VHDL model of the FOT processor generator was built, based on which it was possible to synthesize IP cores of one- and two-dimensional processors of fast direct and inverse Fourier, Hartley, cosine, sine, etc. transformations for different number of points. The creation of this generator of FOT processors made it possible to repeatedly reduce the time and improve the design quality of the IP cores of the above-mentioned FOT processors.

Later, based on the experience gained, I developed the principles of developing computer device model generators, based on which the Intron team within several projects created several IP core generators, in particular, a generator of data protection processors according to the DES algorithm, a generator of data protection processors according to the AES algorithm, parallel memory generator and others.

The process of designing generators of models of computer devices is very time-consuming and requires a high qualification of the developer. I saw the solution to the problem in creating software tools that would allow IP cores to be automatically generated from the description of an algorithm they are supposed to execute, given by a high-level programming language. Here, two approaches to creating means of automatically generating IP cores from an algorithm were proposed. The first approach involved the compilation of the algorithm from a high-level language to its assembly representation, then the construction of a flow graph of the algorithm, its representation in the form of a structural matrix, based on which, taking into account the technical characteristics, a VHDL model of the processor is synthesized. Following this approach, C2HDL OSCAR tools were created at Intron. The second approach provided for the creation of a basic configuration model of the processor, by configuring which the VHDL model of the processor is synthesized with the values of the technical characteristics of the processor and the assembler program. Using this approach, C2HDL Chameleon tools were created at Intron. The creation of the basic configuration model of the processor and, respectively, the Chameleon tools, became possible owing to the development of a new computing model and a new computer architecture with a spatial-temporal organization of computations.